1. Field of the Invention
The invention relates to a multiplexer which has at least two inputs, at least one output and a clock for the inputs, as disclosed in DE 38 08 036 A1.
2. Description of the Related Art
Multiplexers are used in circuits when the aim is to concentrate a plurality of channels onto one common channel. If one wishes to digitize N analog channels, for example, this normally requires N analog/digital (A/D) converters. Using a multiplexer, all N analog channels can be time-division multiplexed onto a common analog channel and digitized by a single A/D converter. Since N A/D converters are normally more expensive than a single, N times faster A/D converter, this involves a cost saving. Added to this is the fact that the layout of a circuit is significantly simplified by omitting N-1 lines and N-1 A/D converters.
Signal critical applications in magnetic resonance (MR) installations, for example, require the use of multiplexers which meet particularly high demands, since this presupposes that a high signal quality is obtained during the signal processing. Preferably, a multiplexer should have a high level of channel separation for this purpose, so that crosstalk is kept as low as possible. The multiplexer should also be able to process a correspondingly high level of dynamics of at least 100 dB and should be able to be operated at high clock rates in the region of 40 MHz. At a clock rate of 40 MHz, the time for turning on and off should be no more than 5 ns, assuming a turn-on duration of 15 ns. When analog signal compression is used between multiplexer and A/D converter in order to reduce the bit depth of the A/D converter, the multiplexer should be able to suppress the multiplex clock, i.e. the switching clock and many of its harmonics, to a sufficient extent, since otherwise the compressor is being modulated in the nonlinear range, and the expansion back to the original useful signals becomes erroneous.
Most known multiplexers are integrated chips and are based to a large extent on CMOS technology. Normally, however, they do not meet at least one of the demands mentioned above. By way of example, although the four-to-one multiplexer MAX4559 from Maxim Integrated Products, Inc. has a channel separation of 60 dB and above at 2 MHz, it requires approximately 150 ns just for turning on or off. The series ADG781, ADG782 and ADG783 multiplexers from Analog Devices, Inc., with a turn-on time of 16 ns and a turn-off time of 10 ns, are an order of magnitude faster than the aforementioned multiplexers, which nevertheless does not meet the demands cited above. Even the switching clock suppression does not meet these high demands in all of the examples cited.
DE 38 08 036 A1 discloses a multiplexer for combining four digital signals over time to form one output signal. In this case, the multiplexer contains four signal transistors which each have an emitter connection, four clock transistors which each have two emitter connections, and a multi-emitter transistor with four emitter connections. In this arrangement, the emitters of the signal transistors are connected in a particular manner to the emitters of the double emitter clock transistors and to the four emitter connections of the four-way multi-emitter transistor. The collector connection of the multi-emitter transistor is the signal output of the multiplexer in this case. To generate balanced output signals, an emitter-coupled differential amplifier may be connected to the signal output. For this multiplexer circuit based on emitter followers, however, there is no provision for switching clock suppression and no provision for multiplexing analog signals.
In the field of electronic balanced and bridge mixers, “ring modulators”, balanced or bridge arrangements of symmetrical design are known for suppressing a local oscillator signal (cf. book by Zinke, Brunswig: “Hochfrequenztechnik 2” [Radio-frequency engineering 2], 5th Edition, Springer-Verlag (DE), 1999, pages 492 to 494). Problems with such mixers cannot readily be transferred to multiplexers.